1. Field of the Invention
The present application relates to programmable logic devices, and more particularly to a bypass-able carry chain in a programmable logic device.
2. Related Art
A programmable logic device (“PLD”) is a digital, user-configurable integrated circuit used to implement a custom logic function. For the purposes of this description, the term PLD encompasses any digital logic circuit configured by the end-user, and includes a programmable logic array (“PLA”), a field programmable gate array (“FPGA”), and an erasable and complex PLD. The basic building block of a PLD is a logic element (LE) that is capable of performing logic functions on a number of input variables. A LE is typically equipped with circuitry to programmably implement the “sum of products” logic or look-up table logic, as well as one or more registers to implement sequential logic. Conventional PLDs combine together large numbers of such logic elements through an array of programmable interconnects to facilitate implementation of complex logic functions. PLDs have found particularly wide application as a result of their combined low up front cost and versatility to the user.
In a typical PLD architecture, an arithmetic mode of the LE is provided to implement faster arithmetic. In this mode, carry-chain logic is used between LEs to provide a fast rippling carry chain through a series of LEs, with each LE implementing a bit-slice of the arithmetic.
For example, with reference to FIG. 1, a typical PLD architecture 100 is depicted. PLD architecture 100 includes an array of logic elements (LEs) 102. Sets of LEs 102 are grouped together as logic array blocks (LABs) 104. A LAB 104 includes a carry chain 108, which connects the set of LEs in LAB 104. As depicted in FIG. 1, a carry-input signal (Cin) enters through the first LE 102 in LAB 104, propagates serially through each LE 102, then a carry-out signal (Cout) exits through the last LE 102. Because carry chain 108 propagates serially through each LE 102 in LAB 104, each LE 102 within LAB 104 is forced to be in arithmetic mode, unless carry chain 108 is broken within LAB 104. Breaking a carry chain 108, however, can increase the delay for the logic and result in waste since the LEs 102 following the break in the carry chain 108 can not be used to perform other functions.
As also depicted in FIG. 1, PLD architecture 100 includes a number of input lines 106 into LAB 104. The number of input lines 106 for a LAB 104 is typically determined based on the typical usage rather than the maximum usage of LAB 104. Thus, a complex arithmetic operation may require more inputs per LE 102 than the typical usage, which can result in insufficient number of input lines 106 to fully support the carry chain.